1996

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Journal paper
  1. Takeo YOSHIDA, Hitoshi KIYA, Sachio NAITO,
    "Design Verification for Register Transfer Level Design by Input Label Sets and Control Conditions,"
    IEICE Trans.,
    vol.J79-D, no.1, pp.28--40, January, 1996.
    [webpage] [Local]
  2. Masahiro IWAHASHI, Noriyoshi KAMBAYASHI, Hitoshi KIYA,
    "A Motion Compensation of Scalable Decoder for Drift Reduction,"
    IEICE Trans.,
    vol.J79-A, no.1, pp.125--134, January, 1996.
    [webpage] [Local]
  3. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters Based on Delayed LMS Algorithm,"
    IEICE Trans.,
    vol.J79-A, no.5, pp.1050--1057, May, 1996.
    [webpage] [Local]
  4. Hisashi SAKANE, Hitoshi KIYA,
    "A Super-Resolution Method Based on the Discrete Cosine Transform,"
    IEICE Trans. Fundamentals,
    vol.E79-A, no.6, pp.768--776, June, 1996.
    [webpage] [Local]
  5. Masahiro IWAHASHI, Noriyoshi KAMBAYASHI, Hitoshi KIYA,
    "A Scalable Decoder with Reduced Hardware Complexity,"
    IEICE Trans.,
    vol.J79-A, no.7, pp.1324--1329, July, 1996.
    [webpage] [Local]
  6. Shogo MURAMATSU, Hitoshi KIYA,
    "A New Factorization Technique for the Generalized Linear-Phase LOT and Its Fast Implementation,"
    IEICE Trans. Fundamentals,
    vol.E79-A, no.8, pp.1173--1179, August, 1996.
    [webpage] [Local]
  7. Kazunobu TOGUCHI, Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "Subband Adaptive Filters with Perfect Reconstruction DFT Filter Banks,"
    IEICE Trans.,
    vol.J79-A, no.8, pp.1385--1393, August, 1996.
    [webpage] [Local]
  8. Masahiro IWAHASHI, Noriyoshi KAMBAYASHI, Hitoshi KIYA,
    "Bit Reduction of DCT Basis for Transform Coding,"
    IEICE Trans.,
    vol.J79-B-I, no.53, pp.572--581, August, 1996.
    [webpage] [Local]
  9. Hitoshi KIYA, Hiroyuki KOBAYASHI,
    "Oversampled Filter Banks Based on Polyphase Submatrices,"
    IEICE Trans.,
    vol.J79-A, no.9, pp.1525--1534, September, 1996.
    [webpage] [Local]
  10. Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "A Design Method for Oversampled DFT Filter Banks with the Minimum Delay,"
    IEICE Trans.,
    vol.J79-A, no.11, pp.1801--1807, November, 1996.
    [webpage] [Local]
  11. Shogo MURAMATSU, Hitoshi KIYA,
    "An Efficient Structure of GenLOT for Finite-Duration Sequences and Its Application to M-Band Discrete-Time Wavelet Transforms,"
    IEICE Trans.,
    vol.J79-A, no.12, pp.1966--1976, December, 1996.
    [webpage] [Local]
International conference
  1. Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "Generating a Hierarchical Simulation Model on the Basis of Functional Model of Register Transfers,"
    IEEE International Symposium on Circuits and Systems,
    1st May, 1996.
  2. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters Based on Two-Dimensional LMS Algorithm,"
    International Technical Conference on Circuits/Systems, Computers and Communications,
    1st July, 1996.
  3. Kuniyuki KAJITA, Hiroyuki KOBAYASHI, Shogo MURAMATSU, Akihiko YAMADA, Hitoshi KIYA,
    "Design Methods for Oversampled DFT Filter Banks,"
    International Technical Conference on Circuits/Systems, Computers and Communications,
    1st July, 1996.
  4. Shigenori KINJO, Hiroshi OCHI, Hitoshi KIYA,
    "A New Two-Dimensional Parallel Block Adaptive Digital Filter,"
    IEEE Midwest Symposium on Circuits and Systems,
    1st August, 1996.
  5. Hisashi SAKANE, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "A Super-Resolution Method Based on the Discrete Cosine Transforms,"
    EURASIP European Signal Processing Conference,
    1st September, 1996.
  6. Shogo MURAMATSU, Hitoshi KIYA,
    "A New Design Method of Linear-Phase Paraunitary Filter Banks with an Odd Number of Channels,"
    EURASIP European Signal Processing Conference,
    1st September, 1996.
  7. Kuniyuki KAJITA, Hiroyuki KOBAYASHI, Shogo MURAMATSU, Akihiko YAMADA, Hitoshi KIYA,
    "A Design Method of Oversampled Paraunitary DFT Filter Banks Using House-Holder's Factorization,"
    EURASIP European Signal Processing Conference,
    1st September, 1996.
  8. XiaoXia ZOU, Shogo MURAMATSU, Hitoshi KIYA,
    "The Generalized Overlap-Add and Overlap-Save Methods Using Discrete Sine and Cosine Transforms for FIR Filtering,"
    IEEE International Conference on Signal Processing,
    1st October, 1996.
Domestic conference
  1. Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "Generating a Hierarchical Simulation Model on the Basis of Functional Model of Register Transfers,"
    IPSJ Technical Reports,
    no.DA79-4, 1st February, 1996.
  2. Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "A Design Method of Low Delay DFT Filter Banks,"
    General Conference of IEICE,
    no.A-204, 1st March, 1996.
  3. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters based on Two-Dimensional LMS Algorithm,"
    General Conference of IEICE,
    no.A-142, 1st March, 1996.
  4. XiaoXia ZOU, Hisashi SAKANE, Hitoshi KIYA,
    "Algorithm for the DFT-based Super-resolution Method using,"
    General Conference of IEICE,
    no.A-135, 1st March, 1996.
  5. Yasuhiro HARADA, Shogo MURAMATSU, Hitoshi KIYA,
    "Evolution of Linear-Phase Orthonormal M-band DTWT using the modified GenLOT,"
    General Conference of IEICE,
    no.SA-4--5, 1st March, 1996.
  6. Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "Oversampled DFT Filter Banks with Arbitrary Decimation Ratios and Their Minimum Delays,"
    Technical Report of IEICE,
    no.DSP96-10, 1st May, 1996.
  7. Takuya YAMAUCHI, Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "Low Delay Oversampled Filter Banks,"
    Technical Report of IEICE,
    no.DSP96-42, 1st June, 1996.
  8. Keisuke NAKAZONO, Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "A Unit Selection Method for Multiplications with Various Word Lengths,"
    Technical Report of IEICE,
    no.VLD96-14, 1st June, 1996.
  9. Seiji WATANABE, Kiyoshi NISHIKAWA, Nobuo FUJII, Hitoshi KIYA,
    "A Design Method of Rate Converters based on Adaptive Filters,"
    Technical Report of IEICE,
    no.DSP96-61, 1st July, 1996.
  10. Shogo MURAMATSU, Hitoshi KIYA,
    "An Efficient Structure of Generalized LOT for Finite-Duration Sequences : Efficient implementation of a symmetric extension method,"
    Technical Report of IEICE,
    no.DSP96-62, 1st July, 1996.
  11. Tsukasa YAMAMOTO, Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "None,"
    IPSJ Design Automation Symposium,
    1st August, 1996.
  12. Yasuhiro HARADA, Shogo MURAMATSU, Hitoshi KIYA,
    "Two-Channel QMF Banks without Checkerboard Effect,"
    Technical Report of IEICE,
    no.CAS96-52, 1st September, 1996.
  13. Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "An Evaluation of the Simulation Model with a Hierarchy in terms of Abstraction Levels,"
    Society Conference of IEICE,
    no.A-65, 1st September, 1996.
  14. Hiroyuki KOBAYASHI, Takuya YAMAUCHI, Hitoshi KIYA,
    "Oversampled Filter Banks with Arbitrary Delays,"
    Society Conference of IEICE,
    no.A-74, 1st September, 1996.
  15. Seiji WATANABE, Nobuo FUJII, Hitoshi KIYA,
    "A Design Method of Multistage Rate Converteres based on Adaptive Filters,"
    Society Conference of IEICE,
    no.A-93, 1st September, 1996.
  16. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "An Architecture of Pipelined Adaptive Filters Using A New Look-ahead transformation,"
    Society Conference of IEICE,
    no.A-94, 1st September, 1996.
  17. Seiji WATANABE, Hitoshi KIYA, Nobuo FUJII,
    "A Design Method of Multistage Rate Converteres based on Adaptive Filters,"
    IEICE Digital Signal Processing Symposium,
    no.B3-3, 1st November, 1996.
  18. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters Based on Look-Ahead-Based Delayed LMS Algorithm,"
    IEICE Digital Signal Processing Symposium,
    no.A6-1, 1st November, 1996.
  19. XiaoXia ZOU, Shogo MURAMATSU, Hitoshi KIYA,
    "Implementation of Sampling Rate Conversion with Fewer Delay,"
    Technical Report of IEICE,
    no.DSP96-104, 1st December, 1996.
Others